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phy1078 - 01 - rd - 1.2 datasheet page 1 125m bps C 2.5 g bps fttx burst mode laser driver / postamplifier features ? burst - mode common anode laser driver with up to 80ma modulation and 90 ma bias current ? 7ns output switching in burst mode ? power saving mode with zero bias and modulation current between bursts ? closed or open loop bias mode with temperature lookup table ? temperature compensated modulation current ? limiting amplifier with programmable low pass filter and output swing ? device settings stored in external 2k eeprom a pplications ? gepon ? bpon description the phy1078 - 01 is a combined burst mode laser driver and limiting amplifier for use within fiber optic modules for fttx a pplications. used with the phy1095 or phy1097 transimpedance amplifier s and a low cost serial eeprom it forms a complete pon diplexer silicon solution. the transmit block in cludes a high frequency modulator and a bias current generator. the bias current can be controlled either by a fast settling apc loop or in open loop mode which uses a temperat ure lookup table. the receive r includes a limiting amplifier with programmable bandwidth. a signal detect/loss of s ignal function is implemented using the input signal modulation amplitude with user selectable threshold and hysteresis. operating with a 3. 3v supply and rated from - 40 to +9 5c ambient, the phy1078 - 01 is housed in a 32pin, 5x5mm, rohs compliant, t qfn package. eeprom_sda 1 sda vss_rxo rxout- rxout+ rref vdd_txo laser- vss_txo vss_txo vdd_txo bias eeprom_scl vdd_rxo vdd_rx vss_rx rxin- rxin+ sd/los tsense tx_fault tx_disable txin+ ben+ mpd laser+ vdd_tx 32 scl vss_rx ben- vss_ic txin- figure 1 C block diagram figure 2 C device pin out phy1078 - 01 19 - 56 85 ; rev 8 /1 2 a maxim integrated products brand
phy1078 - 01 - rd - 1.2 datasheet page 2 contents 1. ordering information ................................................................................................................... 3 2. pin d escription ............................................................................................................................ 3 3. key specifications ....................................................................................................................... 5 3.1. absolute maximum ratings ................................................................................................ . 5 3.2. continuous ratings ............................................................................................................. 5 3.3. receiver .............................................................................................................................. 5 3.4. transmitter .......................................................................................................................... 7 3.5. 2- wire serial interface ....................................................................................................... 10 4. functional description ............................................................................................................... 12 4.1. overview ........................................................................................................................... 12 4.2. receiver features ............................................................................................................. 12 4.3. transmitter features .......................................................................................................... 15 4.4. laser safety features ....................................................................................................... 20 4.5. temperature measurement ............................................................................................... 23 5. control in terface ........................................................................................................................ 24 5.1. boot sequence .................................................................................................................. 25 5.2. main control loop ............................................................................................................. 27 5.3. 2- wire serial interface ....................................................................................................... 28 6. register map ............................................................................................................................. 30 7. simplified interface models ....................................................................................................... 42 8. applications information ............................................................................................................ 44 8.1. phy1078 - 01 in an onu application .................................................................................. 44 8.2. power supply connections ............................................................................................... 45 8.3. burst enable and tx input connection options ................................................................ . 46 8.4. laser connection C dc- coupled ...................................................................................... 47 8.5. mean power control loop startup algorithm .................................................................... 48 9. packaging ................................................................................................................................ . 51 10. contact information ................................................................................................................... 53
phy1078 - 01 - rd - 1.2 datasheet page 3 1. ordering information part number description package PHY1078-01-qt-rr fttx laser driver and post amp tqfn32, 5mmx5mm in tape and reel 2. pin d escription pin no name direction type description 1 eeprom _sda i/o lvttl eeprom 2 wire serial interface data, internal 8k pull up 2 vdd_rxo power receiver output power supply 3 vss_rxo ground receiver output ground connection 4 rxout - o/p cml limiting amplifier serial data output 5 rxout+ o/p cml limiting amplifier serial data output 6 sda i/o lvttl 2-wire serial interface data 7 scl i/o lvttl 2-wire serial interface clock 8 rref internal connection, leave open circuit 9 tx_fault o/p lvttl (open collector) laser fail alarm (requires external pull up) 10 tx_disable i/p lvttl laser enable / disable 11 txin+ i/p high speed input laser driver serial input, see section 7 for interfacing details 12 txin - i/p high speed input laser driver serial input, see section 7 for interfacing details 13 vss_ ic internal connection, connect to ground 14 ben + i/p high speed input burst enable positive, see section 7 for interfacing details 15 ben - i/p high speed input burst enable negative, see section 7 for interfacing details 16 mpd i/p analog monitor photodiode input 17 bias o/p analog laser bias current output 18 vd d_tx power driver power supply 19 vdd_txo power driver output power supply 20 vss_txo g rou nd driver output ground connection 21 laser - o/p high speed output laser driver serial output 22 laser + o/p high speed output laser driver serial output 23 vss_txo g rou nd driver output ground connection 24 vdd_txo power driver output power supply 25 tsense i/p analog external temperature component connection
phy1078 - 01 - rd - 1.2 datasheet page 4 pin no name direction type description 26 sd/ los o/p lvttl (open collector) signal detect or loss of signal output (requires external pu ll up ) . polarity selected by user 27 vss_rx ground receiver ground connection 28 rxin- i/p cml limiting amplifier serial data input 29 rxin+ i/p cml limiting amplifier serial data input 30 vss _rx power receiver ground connection 31 vdd_rx power receiver power supply 32 eeprom _scl o/p lvttl eeprom 2 -wire serial interface clock, internal 8k ? pull up ep vss_ep g roun d common ground / thermal pad
phy1078 - 01 - rd - 1.2 datasheet page 5 3. key specifications 3.1. absolute maximum ratings parameter conditions min typ max unit supply voltage -0.5v 6.5 v voltage on any signal pin -0.5 vdd + 0.5v v storage temperature 150 c max junction temperature 140 c max soldering temperature ipc/jedec j- std -020c 260 c esd human body model jesd-22-a114-b 2 kv device not guaranteed to meet specifications, permanent damage may be incurred by operating beyond these limits. 3.2. continuous ratings parameter conditions min typ max unit operating supply voltage continuous operation 2.97 3.3 3.63 v current consumption excluding bias & modulation c urrent at 20ma bias & 20ma modulation 110 130 ma operating temperature case temperature +110 c ambient still air -40 25 +95 c 3.3. receiver 3.3.1. receive limiting amplifier parameter conditions min typ max unit input sensitivity 1.25gbps, prbs 2 7 -1, ber=1 x10 - 12 6 8 mvp -p 2.5gbps, prbs 2 31 -1, ber=1x 10 - 10 7 10 mvp -p system sensitivity 1.25gbps, prbs 2 7 -1, ber=1x10 -12 with phy1095 tia pd responsivity = 0.8a/w, pd capacitance = 0.5pf, er = 10 db -32 dbm 2.5gbps, prbs 2 31 -1, ber=1x10 -10 with phy1097 tia pd responsivity = 0.9a/w, pd capacitance = 0.5pf, er = 10db -29 dbm crosstalk sensitivity penalty imod=20ma, separate tosa and rosa measured on phyworks reference design 0.1 db maximum differential input tj within spec 1200 mvp -p input termination impedance differential 80 100 120 ?
phy1078 - 01 - rd - 1.2 datasheet page 6 parameter conditions min typ max unit input common mode voltage vdd_rx - 1.5 v input l ow frequency cutoff high pass 3db point for rx system 15 khz differential output rise and f all times (20% - 80%) fast slew rate setting, 1250mbps - 2488mbps filter setting 100 ps differential output s wing cml_level = 0 cml_level = 1 700 370 900 470 mvp -p total jitter input voltage swing 30mvp-p, k28.5 pattern 200 muip-p output resistance rxout +/ - single ended to vdd_rxo 40 50 60 ? output return loss differential, f<2ghz, device powered on 10 db rx 3db frequency 125/155 mbps setting 622 mbps setting 1250 mbps setting 2488 mbps setting 120 470 940 1900 mhz 3.3.2. oma los parameter symbol conditions min typ max unit oma los assert time t loss_on 100 s oma los de -assert time t loss_off 20 s electrical hysteresis 20log 10 (vdeassert / vassert) high setting low setting 4 3 db oma los assert level set by oma_ dac, address d9h 10 50 mv squelch assert t ime t squelch_on 100 s squelch de-assert t ime t squelch_off 20 s figure 3 - oma los detection
phy1078 - 01 - rd - 1.2 datasheet page 7 3.4. transmitter 3.4.1. transmitter inputs : txin+/ - , ben+/ - parameter conditions min typ max unit input voltage vilmin 1.14 v vihmax vdd_tx v input swing vpp(diff) 0.2 vpp figure 4 C valid combinations of transmitter input v oltages 3.4.2. laser driver parameter conditions min typ max unit maximum bias current 90 ma bias generator shutdown current tx_disable active or ben disabled 100 a maximum modulation current 80 ma modulation generator shutdown current tx_disable active or ben disabled 100 a electrical 20% to 80% rise / fall time measured using 15 ? ? effective termination, imod = 50ma, ac and dc applications 95 ps electrical overshoot measured using 15 ? ? effective termination, imod = 50ma, 933mhz lpf and tx_driver_cap=20h 5 % electrical pulse width distortion measured using 15 ? ? effective termination, imod = 20 to 50ma 50 ps total jitter contribution measured over modulation current range 150 muip-p laser output compliance range allowed voltage for laser driver output pins in dynamic operation. 600 vdd _tx mv bias current output compliance minimum allowed voltage for pin bias, referenced to ground 500 mv mpd input sink current for correct apc loop operation 2.6 ma mpd capacitance for correct apc loop operation 20 pf
phy1078 - 01 - rd - 1.2 datasheet page 8 3.4.3. burst timings parameter conditions min typ max unit burst enable/disable t ime (electrical) assertion of ben to 90% of desired bias + modulation current de-assert of ben to 10% of settled bias + modulation current target bias current > 10 ma 7 12.8 ns burst length to ensure correct apc loop operation 512 ns initial mean power control settling time from power up or negation of tx_disable to 90% of desired optical power fast settling algorithm enabled overshoot < 10%, see section 8.5 1.2 s 3.4.4. fault timing parameter symbol condition min typ max unit time to initialize t init from power on or application of vdd>2.97v during plug in 300 ms hard tx_disable assert time t off time from rising edge of tx_disable to when the optical output falls below 10% of nominal 5.5 s hard tx_disable negate time t on time from falling edge of tx_disable to when the modulated optical output rises above 90% of nominal 1 ms hard tx_fault assert time t fault time from fault to tx_fault on bias/temperature adc outside safe range all other fault conditions 10 100 ms s tx_disable pulse width t reset time tx_disable must be held high to reset tx_fault 5 s
phy1078 - 01 - rd - 1.2 datasheet page 9 tx _ fault vdd >2. 97 tx _ disable bias t init t off t on figure 5 - device turn on figure 6 - fa ult detection 3.4.5. eye safety internal fixed limits paramete r symbol comment min typ max unit high supply voltage assert limit v eyeh a applies to vdd_txo or vdd_tx 4.0 4.15 4.3 v high supply voltage de-assert limit v eyeh d 3.7 3.85 4.0 v low supply voltage assert limit v eyel a 2.45 2.6 2.75 v low supply voltage de-assert limit v eyel d 2.7 2.8 2.95 v high supply hysteresis - 0.1 v low supply hysteresis 0.1 v
phy1078 - 01 - rd - 1.2 datasheet page 10 3.4.6. power on reset (por) parameter symbol comment min typ max unit power on reset (por) entry voltage v entry reset is low input voltage 0.5 v por entry reset time t reset time vcc is held low 1.0 ms power on reset (por) exit voltage v e xit 1.2 v por exit delay t delay time before first eeprom access 8.0 ms 3.0v 0v vcc t reset v entry t delay v exit figure 7 C por timing 3.5. 2- wire serial interface 3.5.1. ac electrical characteristics p arameter symbol comment min typ max unit scl clock frequency f scl 0 100 khz low period of the scl clock t low 4.7 s high period of the scl clock t high 4.0 s set-up time for a repeated start condition t su:sta 4.7 s hold time (repeated) start condition t hd:sta 4.0 s data hold time t hd:dat 0 3.45 s data set-up time t su:dat 250 ns rise time of both sda and scl signals t r 1000 ns fall time of both sda and scl signals t f 300 ns set-up time for stop condition t su:st o 4.0 s bus free time between a stop and start condition t buf 4.7 s output fall time from v ihmin to v ilmax t of 10pf < c b (1 ) < 400pf 0 250 ns capacitance for each i/o pin c i 10 pf 1: c b = capacitance of a single bus line in pf.
phy1078 - 01 - rd - 1.2 datasheet page 11 t su : dat t hd: dat t r t f t su : sto t buf sda scl figure 8 - sda and scl bus timing 3.5.2. dc electrical characteristics parameter symbol comment min typ max unit low level input voltage v il -0.5 0.3vdd v high level input voltage v ih 0.7vdd vdd+0.5 v low level o/p voltage v ol 3 ma sink current 0 0.4 v i/p current each i/o pin i i 0.1v dd < v i < 0.9v dd -10 10 ma power on reset (por) voltage reset is low input voltage 0.5 v por time to reset 1.0 ms 3.5.3. lvttl i/o p ins 1 parameter comment min typ max unit lvttl voltage out high external 4.7k to 10k pullup 2.4 v lvttl voltage out low external 4.7k to 10k pullup 0.4 v lvttl voltage i n high internal pullup 2.0 vdd - 0.2 v lvttl voltage in low internal pullup 0 0.8 v internal pull-up resistance , eeprom_sda, eeprom_scl 6 10 k ? 1 applies to lvttl pins specified on pages 3-4
phy1078 - 01 - rd - 1.2 datasheet page 12 4. functional description 4.1. overview figure 9 - phy1078 - 01 functional overview 4.2. receiver features the phy1078 - 01 receiver section consists of an automatic gain control (agc) input amplifier, which is fol lowed by a programmable low pass filter. the filtered signal is passed to a limiting stage and the receiver output is a cml driver. offset cancellation is provided by dc - feedback. a signal detect (sd)/ l oss o f s ignal (los) alarm is provided to detect if the amplitude of the ac - signal at the receiver input is below a programmable threshold. for a transimpedance amplifier with a constant gain, the los threshold corresponds to a particular o ptical m odulation a mplitude (oma) . 4.2.1. receiver input stage the receiver input stage includes internal 50 ? single - ended termination resistor s and is designed to be ac - coupled to the transimpedance amplifier. by default the receiver is non - inverting ; however , to simplify the pcb layout of differential signals the polarity of the data can be inverted by setting rx_polarity (c3h, rx_limiter , bit 1) to 1.
phy1078 - 01 - rd - 1.2 datasheet page 13 4.2.2. receiver filter the programmable low pass filter provides band limiting in the receive signal path and can be used to improve the system sensitivity when a higher bandwidth tia is used. the bandwidth of the fil ter is set to 0.7 x signal data rate selected and is controlled by a 3 - bit control word as follows: bit 2 1 0 data rate 0 0 0 125/155mbps 0 0 1 622mbps 0 1 0 reserved 0 1 1 1.250gbps 1 0 0 2.488gbps table 1- receive filter data rates the 3 - bit control word is set in the rate_select register (c4 h, rx_filter , bits 2:0). 4.2.3. receiver cml output stage the cml output stage has two slew rate settings, selected by cml_slew (c5h , rx_driver , bit 1). the switching speed can be reduced in order to minimise electromagnetic radiation by setting cml_slew to a 1 . s et ting cml_slew to 0 maximises the slew rate of the output . the signal swing can also be adjusted . setting cml_level to 0 (c5h , rx_driver , bit 0) re sults in a higher receiver differential output swing. set ting cml_level to 1 results in a reduce d output swing . rxout+/ - can also be disabled by setting rx_squelch to a 1 (c2h, rx_agc, bit 2). the phy1078 - 01 can automatically disable rxout +/ - if a los condition is detected. to enable this function los_to_squelc h should be set to 1 (c2h , rx_agc , bit 3). in both cases the output termination remains as 50 ? but a logical 0 is output on rxout+/ -.
phy1078 - 01 - rd - 1.2 datasheet page 14 4.2.4. loss of signal oma based los rxin - am plitude detect oma _ dac d9h sd / los rx _ muxpol c6h bit 0 mux _ polarity hware _ sense _ status ech bit 3 los figure 10 - los detection signal detect (sd) or loss of s ignal (los) is detected by measuring the optical modulation amplitude (oma). the signal amplitude measured at rxin+/ - is compared to an analog threshold level set by the oma_dac register (d9h , oma_dac). if the received signal amplitude does not exceed the threshold then the los pin is asserted and the los indicator bit is set (ech , hware_sense_status , bit 3). the polarity of the los pin and register indicator bit are controlled by mux_polarity (c6h , rx_muxpol , bit 0). if mux_polarity is set to 0 then the los pin is set high during a loss of signal condition. conversely, if mux_polarity is set to 1 then the los pin is set high when a sig nal is detected. los detection has hysteresis, the level of which can be selected by omahystsel (c6h , rx_muxpol , bit 1). if omahystsel is set to 0 then 3db of hysteresis is used. if omahystsel is set to 1 then 4db of hysteresis is used. parameter comm ents step size dac range operational range oma_ dac oma los dac (8 bits) 250 v (125 v) 0 to 64mv 10mv to 50mv table 2 - los dac characteristics 4.2.5. voltage reference the phy1078 - 01 includes a temperature stable 1v reference source which provides the bias for the internal analog circuitry. the reference voltag e is set us ing an internal resistor rinternal (ceh, dac _ pwrd, bit 5) to 1 . the accuracy of the reference voltage using the internal resistor is +/ - 10%.
phy1078 - 01 - rd - 1.2 datasheet page 15 4.3. transmitter features the transmitter input buffer provides the necessary drive to the laser driver output stage. it includes a n internal high impedance bias network and is designed to be dc or ac - couple d. for high frequency applications an external termination network must be implemented . s ee section 7 for more interfacing details. the laser driver output is designed to drive lasers in the common anode configuration using either ac - or dc - coupling. for burst mode operation dc - coupling must be used. the laser driver circuit delivers a maximum peak to peak modulation current of 8 0ma measured at the device output pin laser +. by default the transmitter is non - inverting ; however , to simplify the pcb layout of differential signals the polarity of the data can be inverted by setting tx_polarity (cah, tx_ dbuff , bit 0) to 1. 4.3.1. modulation current control figure 11 - modulation current generation the modulation current can be either set by a constant register value or controlled by a temperature indexed look - up table (lut). if mod_temp_disable is set to 1 (d0h , tx_biasloop_control , bit 7) then the modulation d ac is set directly from a register (d4h , mod_dac). if mod_temp_disable is set to 0 then a 64 byte lut is used to set the modulation dac. the lut is indexed by the temperature adc (e1h , temp_adc_value), where the index is given by: index = (temperature adc x 64)/25 5. the values of the lut reside in the eeprom , between addresses 80h (lowest temperature entry) and bfh (highest temperature entry) , and are transferred at start up to on - chip registers . the active setting for the modulation dac can be observed by reading mod_dac_observe (f0h).
phy1078 - 01 - rd - 1.2 datasheet page 16 parameter comments step size dac range operational range imod _dac modulation current dac (8 bits) 0.375ma (1 87 a) 0 to 96ma 0ma to 80ma table 3 - modulation dac characteristics 4.3.2. bias current control figure 12 - bias current generation the phy1078 - 01 can operate with open or closed loop bias control. in either mode the current setting for the bias dac can be obs erved by reading bias_dac_observe (efh). the bias curren t level is measured using an on - chip adc and can be observed by reading bias_adc_value (e2 h ). parameter comments step size adc range operational range ibias_adc bias current adc (8 bits) 0.588ma ( 0.294 ma) 0 to 150ma 0ma to 90ma table 4 - bias adc characteristics parameter comments step size dac range operational range ibias_dac bias current dac (8 bits) 0.392ma (0.196ma) 0 to 100ma 0ma to 90ma table 5 - bias dac characteristics 4.3.3. open loop if op enloop is set to 1 (cch , tx_biasloop , bit 4) the bias generator operates in open loop mode. the bias current can be either set by a constant register value or controlled by a temperature indexed look up table (lut). if bias_temp_disable is set to 1 (d0h , tx_biasloop_control , bit 6) then the bias dac is set directly from a register (d8h , bias_dac).
phy1078 - 01 - rd - 1.2 datasheet page 17 if bias_temp_disable is set to 0 then a 128 byte lut is used to set the bias dac. the lut is indexed by the temperature adc (e1h), where the index is given b y: index = (temperature adc x 128)/ 255 . the values for the lut reside in the eeprom , between addresses 00h (lowest temperature entry) and 7fh (highest temperature entry), and are loaded into on - chip registers at start up. in open loop mode the mpd device pin is not used and can be left unconnected . figure 13 - bias current generation, open loop 4.3.4. closed loop if openloop is set to 0 the bias generator operates in closed loop mode. the average output power of the laser is controlled by a digital mean power control loop . t he feedback to the control loop is provided by a monitor photodiode connected to mpd. the c urrent from the monitor photodiode is compared with a reference current (imonset). this is output by the m ean p ower dac and controlled by mon_dac ( d5h). in order to provide the required resolution and range the m ean p ower dac has three step sizes as shown in the table below. parameter comments step size and resolution range imonset mean power dac (8 bits). mon_dac 31 = 1.042 a (0.5 a) 32 mon_dac 127 = 4.167 a (2 a) mon_dac 128 = 16.67a (8a) 0 to 2.55ma table 6 - mean power dac characteristics the 3db frequency of the digital mean power control loop is controlled by the size of a prescaling counter and can be determ ined (in h ertz) by: f 3db = (kfactor x 692) / (m x imonset)
phy1078 - 01 - rd - 1.2 datasheet page 18 where kfactor = l aser current to monitor photodiode current coupling coefficient imonset = desir ed monitor photodiode current ( a) m = 2 ( 2 x prescale_ size) prescale_size is set b y (d0h, tx_biasloop_control, bits 2:0) . figure 1 4 - bias current generation, closed loop 4.3.5. initial start - up at power up or after tx_disable is de - asserted the phy1078 - 01 can use a fast startup algorithm to quickly settle the mean power control loop to th e desired bias level. the algorithm can only be invoked in closed loop, dc - coupled mode and after it has completed the low bandwidth digital mean power control loop takes over to maintain the optical output power. the details of the startup algorithm and its parameters are described in section 8 .5 . 4.3.6. burst mode and power saving in burst mode operation de - asserting the ben+/ - inputs causes the mean power control loop to pause and turning off the bias current . this mode of operation saves power compared with burst laser drivers that maintain a diverted bias current during burst off. the saving can be up to 95% of the bias and modulation current during burst off periods for a system with a split ratio of 16:1. re - asserting the ben+/ - input re - enables the modulation current and releases the mean power control loop such that the bias current from the end of the preceding burst is used as the start point for the next burst. the burst on/off timings are detailed in the electrical timings section. the polarity of th e ben+/ - inputs can be inverted using burst_polarity (cah , tx_dbuff , bit 2).
phy1078 - 01 - rd - 1.2 datasheet page 19 4.3.7. laser driver setup there is a trimming network on the output driver which adjusts the time constant of the output damping on laser +/ - . it is controlled by the value in tx_dr ive r _cap (c9h). table 7 contains the valid register settings and the damping time constant they set, where rc = 16.8 ps. tx_drive_cap value time constant 00h 0 01h rc 02h 3rc 04h 5rc 08h 6rc 10h 7rc 20h 8rc table 7 - time constant selection for the transmit output damping network 4.3.8. performance monitoring as part of its main control loop the phy1078 - 01 monitors temperature and transmit bias current via an on- chip adc. the adc values are reported via registers temp_adc_value (e1h) and b ias_adc_value (e 2h) . the user has the option of us ing the measured values of temperature and bias current to set alarm bit s. the se are generated if the values measured are above or below programmable limits. the conditions are shown in table 8 and 9 below. temp_max_alarm _en (dah alarm_en bit 3) temp_min_alarm_en (dah alarm_en bit 2) condition temp_max_error (eah bit7) temp_min_error (eah bit 6) 1 x temp_adc_value > temp_max (dbh) 1 0 x x temp_min (dch)< temp_adc_value < temp_max (dbh) 0 0 x 1 temp_adc_value < temp_mi n (dch) 0 1 0 0 x 0 0 table 8 - over and under temperature alarm generation
phy1078 - 01 - rd - 1.2 datasheet page 20 bias_max_alarm_en (dah alarm_en bit 1) bias_min_alarm_en (dah alarm_en bit 0) condition bias_max_error (eah bit 5) bias_min_error (eah bit 4) 1 x bias_adc_value > bias_max (dd h) 1 0 x x bias_min (deh) < bias_adc_value < bias_max (ddh) 0 0 x 1 bias_adc_value < bias_min (deh) 0 1 0 0 x 0 0 table 9 - bias current alarm generation an out of range monitored temperature (temp_max_error is set to 1 or temp_min_error is set to 1) will cause a tx_fault condition to be raised. an out of range monitored bias current (bias_max_error is set to 1 or bias_min_error is set to 1) will cause a tx_fault condition to be raised. the response of the phy1078 - 01 to an alarm condition is described in section 4.4 . 4.4. laser safety features temp_max/min_error bits 7/6 status eah tx_fault temperature monitor bias monitor bias_max/min_error bits 5/4 a from tx_shutdown circuit figure 15 controller logic integrity_fail_e bit 4 debug_events edh dma_fail_e bit 3 soft_tx_fault bit 2 tx_disables e8h fault_latch_en bit 4 alarm_enable dah latch b to tx_shutdown circuit figure 15 0 1 tx_fault bit 3 status eah boot_fail_e bit 2 figure 1 5 - transmit fault generation the laser safety circuit monitors the device for potential faults. if a fault is detected the pin tx_fault is asserted. the register bit tx_fault (eah , status , bit 3) reflects the status of the pin tx_fault. using bias alarm requires fault_latch_enable to be set to 0 .
phy1078 - 01 - rd - 1.2 datasheet page 21 a transmit fault can be raised by the following: 1. the temperature monitor detects that the measured temperature has gone out of range (see section 4.3. 8). 2. the bias current monitor detects that the measured transmit bias current has gone out of range (see section 4 .3. 8). 3. the internal controller logic detects that a dma from eeprom has failed (see section 5 .1 ) 4. the soft_tx_fault bit (e8h , tx_disables , bit 2) is set to 1 5. the voltage reference monitoring circuit detects that the reference voltage is incorrect 6. the supply monitoring circuit detects that the power supply voltage is incorrect if fault_latch_en = 0 (dah , alarm_enable, bit 4) then a transmit fault condition will cause the tx_fault pin to stay asserted even if the fault condition goes away. the pin will stay asserted until either the chip is power cycled or the pin tx_disable is set to 1 or the register soft_tx_disable is set to 1 (e8 h, tx_disables , bit 1) or fault_latch_en is set to 1. if fault_latch_en = 1 then the tx_fault pin is deasserted when the fault condition goes away. figure 16 - transmit shutdown generation the phy1078 - 01 contains circuitry to shutdown the transmitter bias and modulation current if a problem is detected. the conditions to cause a shutdown are: 1. the voltage reference monitoring circuit detects that the reference voltage is incorrect 2. the supply monitoring circuit detects that the power supply voltage is incorrect
phy1078 - 01 - rd - 1.2 datasheet page 22 3 . the soft_tx_disable bit (e8h, tx_disables, bit 1) is set to 1 4 . the internal controller logic has not successfully completed its initialisation (see section 5 .1 ) 5. the pin tx_disable is asserted 6. tx_fa ult is active and fault_powerdown_en = 1 (dah alarm_en bit 5) if a shutdown condition occurs the modulation and bias currents are disabled. conditions 1 -4 can be disabled from contributing to shutdown by setting eye_safety_disable = 1 (cch, tx_biasloop , bit 0). this feature should be used with great caution. the polarity of the tx_disable pin can be inverted by setting tx_disable_polarity (cch, tx_biasloop, bit 7). the register bit tx_shutdown (eah, status, bit 2) reflects the status of the shutdown ci rcuit. the register bit tx_disable (ech, hware_sense_status, bit 4) reflects the status of the pin tx_disable (after optional inversion using tx_disable_polarity ).
phy1078 - 01 - rd - 1.2 datasheet page 23 4.5. temperature measurement the phy1078 - 01 uses an on - chip 8 bit adc to perform a temperature measurement once per iteration of its main control loop (approximately every 10ms). the measured adc value can be read from register temp_adc_value (e1h). this measurement can be used to control the modulation and bias currents. the temperature is determined by forcing two different currents through a diode connected transistor (base and collector shorted together) measuring the resulting voltage difference, ? v be . this voltage is directly proportional to the temperature. if npn_internal is set to 1 (c bh, tx_tempsense, bit 1) then an on - chip transistor is used. in this case pin tsense should be left unconnected. if npn_internal is set to 0 then the adc uses a suitable external device connected to pin tsense. the transistor can be any standard npn silicon transistor with a beta > 100, however phyworks recommends using a bc847b or similar. where accuracy improvement is needed calibration and averaging of the temperature sensor values are recommended or use of an external temperature sensor such as that in a microcontroller. select_3i (cbh, tx_tempsense, bit 0) and vtoislopesel (cbh, tx_tempsense, bits 2 - 3) can be adjusted, depending on the external device used, to ensure that the phy1078 - 01 is capable of measuring the required range of temperatures. the internal temperature sensor operating range is shown in table 10 . ? v be tx _ tempsense bit 0 cbh select 3i tx _ tempsense bi t 1 cbh npn _ internal bc 847b tsense figure 1 7 C temperature sensor functional block diagram parameter comment symbol min typical max units temperature t -45 90 c adc slope vtoislopesel = 00 0.67 c/bit vtoislopesel = 0 1 1.32 c/bit vtoislopesel = 10 1.63 c/bit vtoislopesel = 11 2.25 c/bit tsense delta input voltage vtoislopesel = 0 0 ? v be 50 100 mv table 10 C internal temperature measurement
phy1078 - 01 - rd - 1.2 datasheet page 24 5. control interface twi master twi slave internal registers arbiter 4 3 controller 1 2 host scl sda eeprom eeprom _ scl eeprom _ sda figure 18 - serial interfaces to internal registers the host communicates with the phy1078 - 01 and the eeprom via the slave two w ire i nterface (twi) pins of the phy1078 - 01 . s lave addresses a0h and a2h are supported , register settings for phy1078 - 01 are stored in a2h . if a tra nsaction arriving at the slave interface is addressed to a2h, then the phy1078 - 01 examines the register address in order to decide how the transaction should be processed (se e address map in figure 19). ? if the register is implemented in eeprom only (addresses 00h to bfh) then the transaction is forwarded to the eeprom via path 4 in figure 18 . there is a direct combinational logic path between the slave and maste r interfaces which makes the phy1078 - 01 transparent when transactions from the host are forwarded to the eepro m. ? if the reg ister is only implemented internally to the phy1078 - 01 (addresses e0h to ffh) then the data is written to or read from the registers inside the phy1078 - 01 (path 3). ? if the register is implemented both internally and eeprom (addresses c0h to dfh) then the phy1078 - 01 checks the internal_access register bit (e7h internal bit 1) to determine whether the host wishes to access the eeprom or internal registers . set internal_access is set to 1 to access the internal registers and 0 to access the ee prom. when the phy1078 - 01 comes out of reset, the state machine us es the master two wire interface to read configuration bytes out of eeprom. this data is used to configure the internal registers of the device (path 1). subsequently, during normal operation t he state machine will use the master interface to periodically access look - up table and alarm threshold information stored in the eeprom (path 2). in order to prevent collisions between state machine and host accesses to eeprom , the host must always sto p the state machine before attempting to access the eeprom by setting an internal register bit, sm_stop, to 1 (e7h, internal, bit 0). when the host has completed its transactions with the eeprom it must set sm_stop to 0 to allow normal operation of the state machine to resume . if the host attempts to access the eeprom when sm_stop is set to 0 then writes are ignored and reads return a zero.
phy1078 - 01 - rd - 1.2 datasheet page 25 reads / wr ites to inter nal r egister s internal _ access = 1 inter nal _ access = 0 sm _ stop = 0 sm _ stop = 1 r eads / writes to inter nal r egisters r eads r eturn zero wr ites ignored r eads / writes to eeprom sm _ stop = 0 sm _ stop = 1 r eads r etur n zero writes ignored reads / writes to eeprom address tar get not accessible not accessible not accessible inter nal eeprom 0 -7f 80 - bf c 0 - df e 0 - ff boot configur ation register s control and status register s bias / tem per atur e lookup table m odulation / tem per atur e lookup table boot configuration register s 0 - bf c 0 - df e 0 - ff address figure 19 - phy1078 - 01 twi slave accesses 5.1. boot sequence power up tr ansfer data from eeprom to internal register s dma fail integr ity fail set boot complete m ain loop set boot _ fail _e set integrity _ fail _e set tx _ fault error flag (s) clear ed yes no yes yes no clear tx _ fault figure 20 - phy1078 - 01 boot sequence at power up th e phy1078 - 01 attempts to read a number of bytes of configuration information from an external eeprom into its internal registers.
phy1078 - 01 - rd - 1.2 datasheet page 26 if the read fails due to a problem on the twi, such as a read not being correctly acknowledged, the state machine sets register bit boot_fail_e to 1 (edh , debug_events , bit 2), raises a transmit fault condition and remains in an error state. the first two bytes read from eeprom, c0h and c1h, are compared against a data integrity number (c35ah). if the compare fails , the state machine sets register bit integrity_fail_e to 1 (edh , debug_events , bit 4), raises a transmit fault condition and remain s in an error state. in the error state the host is able to configure the internal registers of the phy1078 - 01 using the slave twi. wh en it has completed configuration the host must clear the active error(s) by writing a 1 to the corresponding bit(s). when the state machine sees that the error bit(s) are cleared it clears the transmit fault condition. the state machine sets the register boot_complete_e (edh , debug_events , bit 1) to indicate that the boot process is complete and then enters the main control loop.
phy1078 - 01 - rd - 1.2 datasheet page 27 5.2. main control loop read adcs m od lut enabled boot seq yes no read m in / m ax thr esholds . set / clear errors accordingly set m od dac to m od / temp lut entry set m od dac to register value open loop yes no bias lut enabled yes no set bias dac to r egister value set bias dac to bias / tem p lut entr y first time yes no clear transmit disable tim er expir ed restar t tim er yes no figure 21 - phy1078 - 01 main loop function a loop timer is implemented in the state machine to ensure that the start of each iteration of the loop is separated by 10ms. when the timer has expired the state machine reads the on - chip adc to obtain temperature and bias current levels, reads alarm levels out of eeprom and sets/clears performance alarms accordingly . the state machine th en sets the modulation current and bias current. at the end of the first iteration of the loop after boot - up the state machine clears transmit disable to enable the transmit data path .
phy1078 - 01 - rd - 1.2 datasheet page 28 5.3. 2-wire serial interface the phy1078 - 01 has a pai r of 2 - wire serial interfaces : a slave for interfacing to a host for module setup and programming , and a master for interfacing to an external eeprom and for device configuration after reset. both interfaces communicate using the protocol described in this section. 5.3.1. framing and data transfer the two - wire interface comprises a clock line (scl) and a data line (sda). when the bus is idle both are pulled high within the phy1078 - 01 by 8k ? pull - ups. an individual transaction is framed by a start condition and a stop condition. a start condition occurs when a bus master pulls sda low while the clock is high. a stop condition occurs when the bus master allows sda to transition low - to - high when the clock is high. within the frame, the master has exclusive control of the bus. the phy1078 - 01 supports repeat start conditions whereby the master may simultaneously end one frame and start another without releasing the bus by replacing the stop condition with a start condition. within a frame, the state of sda may only change when scl is low. a data bit is transferred on a low - to - high transition of scl. data is arranged in packets of 9 bits. the first 8 bits represent data to be transferred (most significant bit first). the last bit is an acknowledge bit. the recipient of the data holds sda low during the ninth clock cycle of a data packet to ack nowledge (ack) the byte. leaving sda to float high on the ninth bit signals a not - acknowledged (nack) condition. the interpretation of the acknowledge bit by the sender will depend on the type of transaction and the nature of the byte being received. 5.3.2. device a ddressing the first byte to be sent after a start condition is an address byte. the first seven bits of the byte contain the target slave address (msb first). the eighth bit indicates the transaction type C 0 = write, 1 = read. each slave interface on the bus is assigned a 7 - bit slave address. if no slave matches the address broadcast by the master then sda will be left to float high during the acknowledge bit and the master re ceives a nack. the master must then assert a stop condition. if a slave identifies the address then it acknowledges the master and proceeds with the transaction identified by the type bit. figure 22 - address decoding example C slave not available 5.3.3. write transaction figure 23 shows an example of a write transaction. the address byte is successfully acknowledged by the slave, and the type bit is set low to signify a write transaction. after the acknowledge the master sends a single data byte. all signalling is controlled by the master except for the sda line during the acknowledge bits. during the acknowledge the direction of the sda line is reversed and the slave pulls sda low to return a 0 (ack) to the master. figure 23 - write transaction 7 1 start ack stop sda scl 4 3 2 1 0 w 7 6 5 msb ack sda direction to slave from slave
phy1078 - 01 - rd - 1.2 datasheet page 29 if the s lave is unable to receive data then it should return a nack after the data byte. this will cause the master to issue a stop and thus terminate the transaction. the phy1078 - 01 interprets the first data byte as a register address. this will be used to set an internal memory pointer. subsequent data bytes within the same transaction will then be written to the memory location addressed by the pointer. the pointer is auto - incremented after each byte. there is no limit to the number of bytes which may be written in a single burst to the internal ram of the phy1078 - 01 . if, however, the write access is destined for the eeprom the requirements of page writes specified for the eeprom apply. if the slave is not ready to receive a byte then it may hold scl low immediately after the acknowledge bit. when scl is released the master starts to send the next byte. this is known as clock stretching. the phy1078 - 01 slave interface will not clock stretch at up to 100 khz scl frequency. 5.3.4. read transaction 7 1 start ack stop sda scl r nack sda direction to slave from slave 7 0 7 0 ack figure 24 - read tran saction figure 24 shows an example of a 2 byte read transaction. the address byte is successfully acknowledged by the slave, and the type bit is set high to signify a read. after the ack the slave returns a byte from the location identified by the internal memory pointer. this pointer is then auto - incremented. the slave then releases sda so that the master can ack the byte. if the slave receives an ack then it will send another byte. the master identifies the last byte by sending a nack to the slave. the m aster then issues a stop to terminate the transaction. thus, to implement a random access read transaction, a write must first be issued by the master containing a slave address byte and a single data byte (the register address) as shown in figure 23 . thi s sets up the memory pointer. a read is then sent to retrieve data from this address (see figure 24 ).
phy1078 - 01 - rd - 1.2 datasheet page 30 6. register map where a single power - on reset (por) value is shown for a range of addresses, that value applies to all bytes in the range. note that the power on reset values may be overwritten during initialisation from the eeprom. for registers containing a single 8 - bit field, the most significant bit of the field is stored in bit 7 of the register byte. note that reserved or internal use only register bits are specified as read only. these registers should not changed from their por default settings. r bit is read only. a write to this bit via the twi will have no effect. the value may be changed by the device itself as part of its normal operation r/w bit is readable and writable via the twi. the value will not be changed by the device itself except under a device reset. e bit is readable via the twi. the bit may be set by the device itself as part of its normal operation. once set the bit may be cleared by writing a 1 via the twi. writing a 0 via the twi has no effect. c0h data_integrity_lower integrity check for eeprom contents. must be set to c3 h for a boot load from eeprom to be successful. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00h c1h data_integrity_upper integrity check for eeprom contents. must be set to 5a h for a boot load from eeprom to be successful. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 0 0h c2h rx_agc this register controls functions in the agc in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 los_to_ squelch r/w 0 setting this bit to a 1 connects th e los function to the receiver squelch such that a los will automatically disable the receiver output 2 rx_squelch r/w 0 setting this bit to a 1 causes the receiver output to be disabled 1 - r/w 0 internal use only. must be set to 0 0 - r/w 0 intern al use only. must be set to 0
phy1078 - 01 - rd - 1.2 datasheet page 31 c3h rx_limiter this register controls functions in the limiter in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 - r/w 0 internal use only. must be set to 0 1 rx_polarity r/w 0 setting this bit to a 1 causes the receive output polarity to be inverted 0 - r/w 0 internal use only. must be set to 0 c4h rx_filter this register controls functions in the filter in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r/w 0 internal use only. must be set to 0 2 rate_select(2) r/w 0 selects the filter rate in the receiver 000 = 155 m bps 001 = 622 mbps 010 = reserved 011 = 1250 mbps 100 = 2488 mbps 1 rate_select(1) r/w 0 0 rate_select(0) r/w 0 c5h rx_driver this register controls functions in the output driver in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 - r 0 reserved 1 cml_slew r/w 0 sets the receiver output slew rate 1 = slow 0 = fast 0 cml_level r/w 0 sets the receiver output swing level 1 = low swing 0 = high swing
phy1078 - 01 - rd - 1.2 datasheet page 32 c6h rx_muxpol this register controls the loss of signal detection circuit in the receive path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 - r 0 reserved 1 omahystsel r/w 0 sets the amount of hysteresis in the los detection circuit 1 = 4 db of hysteresis 0 = 3 db of hysteresis 0 mux_polarity r/w 0 sets the polarity of los output pin 1 = pin is high when signal detect 0 = pin is high when loss of signal c7h test0 internal use only, must be set to 00h type r/w por 00h c8h test1 internal use only, must be set to 00h type r/w por 00h c9h tx_driver_cap this register allows selective snubbing capacitors to be applied to the transmit output stage. setting the register to 0h applies no damping. type r/w por 00 h cah tx_dbuff this register controls functions in the data buffer in the transmit path of the device bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 high_ext(1) r/w 0 this register controls the pedestal current i ped to allow high extinction ratios to be set with consequently reduced rise time. 00 : default , i ped = 0 a , low er, higher speed 01 : i ped = 130 a 10 : i ped = 390 a 11 : i p ed = 520
phy1078 - 01 - rd - 1.2 datasheet page 33 cbh tx_tempsense this register controls functions associated with the device temperature measurement bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 vtoislopesel(1) r/w 0 this field modifies the expected slope from the temperature sensor into the adc and should be set depending on the type of external temperature sensor 2 vtoislopesel(0) r/w 0 1 npn_internal r/w 0 setting this bit to 1 selects the intern al sensor for temperature measurement. setting to 0 selects an external sensor connected to the tsense input pin 0 select_3i r/w 0 setting this bit to 1 causes the temperature sensor to operate at 3 times the default measurement curr ent. cch tx_bia sloop this register controls functions in the bias current generator in the transmit path of the device bit field name type por 7 tx_disable_ polarity r/w 0 setting this bit to a 1 inverts the polarity of the tx_disable input pin 6 - r/w 0 internal use only. must be set to 0 5 - r/w 0 internal use only. must be set to 0 4 openloop r/w 0 sets the configuration of the transmit bias circuit 1 = open loop 0 = closed loop 3 - r/w 0 internal use only. must be set to 0 2 - r/w 0 internal use only. must be set to 0 1 - r/w 0 internal use only. must be set to 0 0 reserved r/w 0 set to 0 during operation of the device cdh test2 internal use only, must be set to 00h type r/w por 00h
phy1078 - 01 - rd - 1.2 datasheet page 34 ceh dac_pwrd bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 rinternal r/w 0 set to 1, an internal 10k ? cfh test3 internal use only, must be set to 00h type r/w por 00h d0h tx_biasloop_control this register controls generation of the transmit bias current bit field name type por 7 mod_temp_ disable r/w 0 setting this bit to 1 disables the modulation current / temperature lookup table 6 bias_temp_ disable r/w 0 in open loop mode setting this bit to 1 disables the bias current / temperature lookup table. in closed loop mode it has no effect 5 burst_start_ factor(1) r/w 0 these bits control the ramp rate used in the closed loop bias current fast startup algorithm. see section 8 .5 for further details 4 burst_start_ factor(0) r/w 0 3 bia s_startup_ bypass r/w 0 setting this bit to 1 disables the fast startup algorithm used for closed loop bias current generation 2 prescale_ size(2) r/w 0 these bits configure the loop bandwidth of the closed loop bias current. see the section 4.3. 4 for f urther details 1 prescale_ size(1) r/w 0 0 prescale_ size(0) r/w 0
phy1078 - 01 - rd - 1.2 datasheet page 35 d1h tx_burst_control this register controls the fast startup algorithm used in the generation of bias current in closed loop mode bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 bs_optimise r/w 0 setting this bit to 1 allows the fast startup algorithm used for closed loop bias current generation to perform an optimisation during its first binary step 2 binary_search _width(2) r /w 0 these bits control the length of time that each step of the binary search sequence of the closed loop bias current fast startup algorithm take s to complete. see section 8 .5 for further details 1 binary_search _width(1) r/w 0 0 binary_search width(0) r/w 0 d2h ramp_step_factor this register controls the ramp rate used in the closed loop bias current fast startup algorithm. see section 8 .5 for further details type r/w por 00 h d3h vref_dac reference voltage trim dac . set to 71h type r/w por 00 h d4h mod_dac sets the modulation current (via a dac) when the modulation / temperature lut is disabled (mod_temp_disable is set to 1) type r/w por 00 h d5h mon_dac sets the target bias current level (via a dac) when the device is in closed loop configuration (openloop is set to 0) type r/w por 00 h d8h bias_dac sets the bias current (via a dac) when the device is in open loop configuration (openloop is set to 1) and the bias / temperature lut is disabled (bias_temp_disable is set to 1) type r/w por 00 h d9h oma_dac sets the threshold level for optical measuremen t amplitude based los detection type r/w por 00 h
phy1078 - 01 - rd - 1.2 datasheet page 36 dah alarm_enable controls the behavio ur of the tx_fault pin and the generation of alarms based on temperature and b ias current levels . bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 fault_powerd own_en r /w 0 if this bit is set to 1 a tx_fault condition will cause the transmitter modulation and bias currents to be shutdown 4 fault_latch_ en r/w 0 if this bit is set to a 0 the output pin tx_fault will remain asserted once a fault condition has been detected even if the fault condition goes away. the pin will remain asserted until either the device is reset or this bit is set to a 1. if this bit is set to a 1 then the output pin tx_fault will be asserted if a fault condition is detected and will be deasserted once the condition is cleared. 3 temp_max_ alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured temperature excee ds temp_max 2 temp_min_ alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured temperature falls below temp_min 1 bias_max alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured bias current exceeds bias_ max 0 bias_min_ alarm_en r/w 0 set this bit to a 1 to enable alarm generation if the measured bias current falls below bias_min dbh temp_max if temp_max_alarm_en is set then this register sets the threshold above which a maximum temperature error is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00 h dch temp_min if temp_min_alarm_en is set then this register sets the threshold below which a minimum temperature error is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00 h ddh bias_max if bias_max_alarm_en is set then this register sets the threshold above which a maximum bias current e rror is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal registers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00 h
phy1078 - 01 - rd - 1.2 datasheet page 37 deh bias_min if bias_min_alarm_en is set then this register sets the threshold below which a minimum bias current error is raised based on the internal adc reading. note, this register exists only in eeprom and not in the internal regist ers of the device, therefore a write to this address when internal_access is set high will be ignored and a read return zero. type r/w por 00 h the following registers exist only in the internal registers of the device. the corresponding addresses in eeprom are unreachable. therefore a twi transaction to these addresses will target the internal device registers regardless of the setting of internal_access. e0h test4 internal use only, must be set to 00h type r/w por 00h e1h temp_adc_value ind icates the current temperature value measured by the internal adc. type r por 00 h e2h bias_adc_value indicates the current bias current value measured by the internal adc. type r por 00 h e3h test5 internal use only, must be set to 00h type r/w p or 00 h e4h test6 internal use only, must be set to 00h type r/w por 00h e5h test7 internal use only, must be set to 00h type r/w por 00h e6h test8 internal use only, must be set to 00h type r/w por 00 h
phy1078 - 01 - rd - 1.2 datasheet page 38 e7h internal this register contro ls the internal state machines used to generate transmit modulation and bias currents bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 bias_sm_reset r/w 0 set this bit to a 1 to put the bias current con trol logic into reset. set to 0 for normal device operation 2 mod_sm_reset r/w 0 set this bit to a 1 to put the modulation current control logic into reset. set to 0 for normal device operation 1 internal _ access r/w 0 set this bit to a 1 to dire ct twi accesses to addresses c0h C dfh to the internal registers of the device. if set to 0 such addresses map to the external eeprom. 0 sm_stop r/w 0 set this bit to a 1 to suspend the internal control logic and allow twi accesses to the external eep rom. if this bit is set to 0 and a twi access is targeted at the eeprom then a write will be ignored and a read will return zero. e8h tx_disables this register controls the transmit safety shutdown circuit. see section 4.4 for further details bit fi eld name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 - r 0 reserved 3 - r 0 reserved 2 soft_tx_fault r/w 0 this bit allows a tx_fault to be declared under control of the twi. setting this bit to a 1 causes a tx_fault condition to be declared 1 soft_tx_ disable r/w 0 this bit allows a tx_disable to be declared under control of the twi. setting this bit to a 1 causes a tx_disable condition to be declared 0 - r/w 0 internal use only. must be set to 0
phy1078 - 01 - rd - 1.2 datasheet page 39 e9h events this regist er contains latched versions of the bits in the status register. if a condition becomes active the bit will report a 1. if the condition goes inactive the bit will stay at 1 until a 1 is written to the bit via the twi bit field name type por 7 tem p_max_ error_e e 0 has value 1 if a maximum temperature error condition has occurred 6 temp_min_ error_e e 0 has value 1 if a minimum temperature error condition has occurred 5 bias_max_ error_e e 0 has value 1 if a maximum bias current error condi tion has occurred 4 bias_min_ error_e e 0 has value 1 if a minimum bias current error condition has occurred 3 tx_fault_e e 0 has value 1 if the output pin tx_fault has been asserted 2 tx_shutdown_ e e 0 has value 1 if a shutdown condition has been detected 1 sm_tx_fault_e e 0 has value 1 if the internal control logic has reported a fault condition 0 sm_tx_disable_ e e 0 has value 1 if the internal control has disabled the transmit circuitry eah status this register reports the status of a n umber of internally monitored conditions within the device. a bit will report a 1 if the condition is active and a 0 if the condition is inactive bit field name type por 7 temp_max_ error r 0 has value 1 if a maximum temperature error condition is currently being detected 6 temp_min_ error r 0 has value 1 if a minimum temperature error condition is currently being detected 5 bias_max_ error r 0 has value 1 if a maximum bias current error condition is currently being detected 4 bias_min_ erro r r 0 has value 1 if a minimum bias current error condition is currently being detected 3 tx_fault r 0 has value 1 if the output pin tx_fault is currently being asserted 2 tx_shutdown r 0 has value 1 if a shutdown condition is currently being asser ted 1 sm_tx_fault r 0 has value 1 if the internal control logic is currently reporting a fault condition 0 sm_tx_disable r 0 has value 1 if the internal control logic is currently disabling the transmit circuitry
phy1078 - 01 - rd - 1.2 datasheet page 40 ebh hware_sense_events this regi ster contains latched versions of the bits in the hware_sense_status register. if a condition becomes active the bit will report a 1. if the condition goes inactive the bit will stay at 1 until a 1 is written to the bit via the twi bit field name ty pe por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 tx_disable_e e 0 has value 1 if the input pin tx_disable changes from 0 to 1 3 los_e e 0 has value 1 if the los detect circuit has detected a los condition 2 - r 0 reserved 1 suppl y _ok_e e 0 has value 1 if the power supply monitoring circuit detects the supply voltage has gone from correct to incorrec t 0 vref _ok_e e 0 has value 1 if the voltage reference monitoring circuit detects the reference voltage has gone from correct to incorrect ech hware_sense_status this register reports the status of various device input pins and detection circuits bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserved 4 tx_disable e 0 indicates the logical status of the input pin tx_disable (after potential inversion according to tx_disable_polarity) 3 los e 0 indicates the status of the los detect circuit. the polarity depends on mux_polarity 2 - r 0 reserved 1 supply _ok e 0 indicates the status of the power supply mo nitoring circuit. if set to 1 then the supply voltage is correct 0 vref_ok e 0 indicates the status of the voltage reference monitoring circuit. if set to 1 then the reference voltage is correct
phy1078 - 01 - rd - 1.2 datasheet page 41 edh debug_events this register indicates whether ce rtain events have occurred within the control logic of the device. if a condition occurs bit will report a 1 and will stay at 1 until a 1 is written to the bit via the twi bit field name type por 7 - r 0 reserved 6 - r 0 reserved 5 - r 0 reserve d 4 integrity_fail_ e e 0 this bit is set to 1 by the device if the boot dma from eeprom fails its integrity check 3 dma_fail_e e 0 this bit is set to 1 by the device if a dma from eeprom does not complete successfully 2 boot_fail_e e 0 this bit is s et to 1 by the device if the boot dma from eeprom does not complete successfully 1 boot_ complete_e e 0 this bit is set to 1 by the device if the boot dma from eeprom completes successfully 0 iteration_e e 0 this bit is set to 1 by the device once p er iteration of the modulation state machine logic (approx every 10ms) efh bias_dac_observe this register indicates the current value of the transmit bias current setting dac type r por 00 h f0h mod_dac_observe this register indicates the current value of the transmit modulation current setting dac type r/w por 00 h ffh chip_id contains a hardwired chip identification number type r por 78 h
phy1078 - 01 - rd - 1.2 datasheet page 42 7. simplified interface models figure 2 5 - transmit input structure figure 2 6 - trans mit output structure figure 2 7 - receive input structure figure 2 8 - receive output structure
phy1078 - 01 - rd - 1.2 datasheet page 43 figure 2 9 - mpd input structure figure 30 - laser bias output structure los, txfault vcc fi gure 3 1 - los/tx_fault output
phy1078 - 01 - rd - 1.2 datasheet page 44 8. applications information 8.1. phy1078- 01 in an onu application figure 3 2 C typical onu application diagram figure 3 2 shows the general connectivity required with the phy1078 - 01 to implement a small form factor (sff) type application, as used in gepon systems. the phy1078 - 01 post amplifier is ac - coupled to the tia in the rosa. dc - coupling is required at the transmitter input and the laser output in order to support burst - mode operation. exact implementation of the matching network varies with the actual laser used. when used in open - loop mode, no monitor photo diode (mpd) will be required in conjunction with the laser. when used in closed loop mode, the mpd is connected to the mpd pin on the phy1078 - 01 . module settings are stored in the eeprom, and can be programmed using the eeprom _sda/scl interface. figure 3 2 shows the use of an external temperature sensor (diode - connected npn - transistor) this should not be used when the internal temperature sensor is used.
phy1078 - 01 - rd - 1.2 datasheet page 45 8.1.1. reference design and firmware checking for the latest reference design and firmware to support phy1078 - 01 is recommended. the documents can be downloaded from the phyworks website or by contacting phyworks representatives. 8.2. power supply connections the phy1078 - 01 has been designed as a low power device. in order to achieve low operating power consumption the transmitter and receiver circuitry in the phy1078 - 01 share some common internal bias circuitry. this requires that the phy1078 - 01 transmitter and receiver be powered up together for correct operation. 8.2.1. pow er supply filtering although the tx vdds and rx vdds should be powered together and therefore, ultimately be connected at a common node, it is beneficial to separately filter the power supplies for the tx vdd and rx vdd supplies. separately filtering the transmitter and receiver supplies off chip will reduce power supply noise and cross talk between the transmitter and receiver C it is generally good practice to separately filter and decouple the individual supplies on any multifunction ic. in addition to supplying separately filtered supplies to the tx vdds and rx vdds of the phy1078 - 01 , it is recommended that any other ics and digital circuitry connected to the phy1078 - 01 in an application environment (e.g. sf f module) be suitably filtered and decoupled. an example of this would be to supply a filtered digital supply for an external mcu. figure 33 C recommended power supply connections and filtering.
phy1078 - 01 - rd - 1.2 datasheet page 46 8.3. burst enable and tx input connection options the phy1078 - 01 supports various modes of interfacing to t he t ransmit data (txin+/ -) and b urst e nable (ben+/ -) inputs providing the signal voltage and common - mode voltage levels are within the valid range specified in figure 4 . some common examples are shown in figures 34-36 below. ? vcc vcc txin+ ben+ txin- ben- 50 ? 50 ? vcc vcc 5k 5k 24k 16k vcc vcc vcc 24k 16k figure 34 - dc- coupled cml interface for txin and ben 82? ? 82? ? figure 35 - dc- coupled lvpecl interface for txin and ben figure 3 6 C single - ended cmos/lvttl interface for ben
phy1078 - 01 - rd - 1.2 datasheet page 47 8.4. laser connection C dc- coupled vcc driver modulation dac bias source bias dac mpc loop burst enable laser+ laser- vcc r series r block r bt bias mpd monitor pd not required for open - loop figure 3 7 - dc - coupled laser application diagram figure 37 shows a typical dc - coupled application. dc current is provided to the output stage via a resistive network. the ac impedance to ground of the laser + pin should be approximately 50 ? to properly terminate that output. r series is used to match the laser impedance. it may also be necessary to use a rc snubbing circuit connected in parallel with the laser to reduce any ringing caused by series inductance in the packaging. a 10 ? resistor , r block , is used to isolate the output stage from the capacitive loading of the bias pin. in this mode, the bias pin can sink up to 80ma of current. for burst - mode applications ferrite s should not be used as they will not allow the bias to settle correctly.
phy1078 - 01 - rd - 1.2 datasheet page 48 8.5. mean power control loop startup algorithm at power up or after tx_disable is de - asser ted the phy1078 - 01 can use a fast startup algorithm to quickly settle the mean power control loop to the desired bias level. a fter the algorithm has completed the low bandwidth digital mean power control loop takes over to maintain the optical output powe r. the algorithm can only be invoked in closed loop, dc coupled mode, for ac coupled applications the startup algorithm must be disabled, and the mean power control loop will settle at a rate determined by its bandwidth. figure 38 - closed loop fast st art - up algorithm the fast start - up algorithm contains three stages as shown in figure 38. stage 1 begins at power - up or after tx_disable is de - asserted and completes when the phy1078 - 01 has successfully loaded its operating parameters from the companion ee prom. during this stage the data path is disabled and the modulation outputs balance d such that i mod /2 flows into both laser+ and laser -. stage 2 is a ramp sequence which starts with an initial step (a) approximately equal to i mod /2 and is followed by sma ller increments (b) on each cycle of the algorithm clock (64mhz) . the ramp continues until an internal comparator detects that the photodiode current has exceeded the desired reference current set by mon_dac (d5h). the finite delay present in the system between setting a bias current and the monitor photodiode current settling means that the bias level at the end of the ramp sequence will have overshot the desired operating point. s tage 3 is a binary search sequence used to quickly and accurately acquire the mean power level. this can take up to eight steps. c ontrol of the bias current is transferred to the low frequency mean power control loop and the data path is enabled at the end of the binary search sequence . there are various parameters within each of the stages which can be controlled by the user : a = imodcode x 0.2662 where a is in ma and imodcode is the value applied to the modulation dac. if a modulation lookup table is used imodcode will be dependant on temperature, otherwise imodecode is equal to the value set in the mod_dac (d4h) register. the actual value applied to the modulation dac is visible in mod_dac_observe (f0h)
phy1078 - 01 - rd - 1.2 datasheet page 49 b = imod code x ramp_step_factor x 0.001512 where b is in ma and the recommended setting for ramp_step_factor (d2h) is 82d. c = imod code x burst_start_factor x 0.2662 where c is in ma and burst_start_factor (d0h, tx_biasloop_control, bits 5:4) can be set between 1 and 3, but 2 is the recommended setting . d = b inary_ s earch _width x 1/f clk b inary_ s earch _width (d1h, tx_burst_contro l_1, bits 2:0) has a valid range of 4 to 8, where 8 is the default and 4 represents fastest binary search time , see table 11 for coding . f clk is 64mhz, the frequency of the internal clock. binary_search_width bit 2 1 0 8 0 0 0 7 1 1 1 6 1 1 0 5 1 0 1 4 1 0 0 table 11 - binary_search_width values at the end of stage 2 the bias current will have exceeded the desired bias level. this overshoot can be estimated using the following equation: max overshoot (ma) < ( l f clk + 1) x ramp_step_factor x imodcode x 0.00 1512 where l is the delay round the a pc feedback loop. for most applications this is dominated by the capacitance of the monitor photodiode (c pd ), so l 250 x c pd . o vershoot can be reduced by lowering the value of ramp_step_factor however this reduction will be at the expense of a longer startup time. the time taken for the algorithm to complete and the parameters used are highly dependent on the optics used in the system. for most systems the default parameter values will be acceptable. the foregoing description assumes that the burst enable signal is always asserted. however , the startup algorithm can be split over up to three bursts . t he algorithm pauses while the burst enable signal is de - asserted and resumes when it is re - asserted. if the algorithm has not completed after three bursts, then control of the bias current is transferred to the mean power control loop using the value reached by the algorithm at the end of the third burst. the mean power control loop settles from that point at a rate determined by its bandwidth. the fast startup algorithm can be disabled by setting bias_startup_bypass (d0h, tx_biasloop_control, bit 3) to 1. if the algorithm is disabled the bias current is initialized to zer o and settles to the desired level a t a rate determined by the bandwidth of the digital control loop.
phy1078 - 01 - rd - 1.2 datasheet page 50 fast startup example for: imod = 30ma imodcode = 80 binary_search_width=4 burst_start_factor=2 c pd = 1 0pf we get: a = 80 x 0.2662 = 21.3ma b = 80 x 82 x 0.001512 = 9.9ma c = 80 x 2 x 0.2662 = 42.6ma d = 4 / fclk = 61ns max overshoot = 1 1.5 ma figure 39 - closed loop fast start - up algorithm example
phy1078 - 01 - rd - 1.2 datasheet page 51 9. packaging figure 40 C 32pin t qfn package dimensions pkg. 32l 5x5 symbol min. nom. max. a 0.70 0.75 0.80 a1 0 0.02 0.05 a2 0.20 ref b 0.20 0.25 0.30 d 4.90 5.00 5.10 e 4.90 5.00 5.10 e 0.50 bsc k 0.25 - - l 0.30 0.40 0.50 n 32 nd 8 ne 8 d2 3.00 3.10 3.20 e2 3.00 3.10 3.20 jedec whhd - 2 packaging notes: 1 . dimensioning & tolerancing conform to asme y14.5m-1994.
phy1078 - 01 - rd - 1.2 datasheet page 52 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 5. nd and ne refer to the number of terminals on each d and e side respectively. 6. co planarity applies to the exposed heat sink slug as well as the terminals. 7. drawing conforms to jedec mo 220. 8. warpage shall not exceed 0.10 mm. 9 . marking is for package orientatio n reference only. 10. number of leads shown is for reference only. 11. lead centerlines to be at true position as defined by basic dimension 'e', 0.05. for the latest package outline information and land patterns (footprints), go to www.maxim - ic.com/pack ages. note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. symbol typical unit thermal resistance C junction to ambient ja 39 c/w thermal resistance C junction to case jc 31 c/w note: refer to eia/ jedec standard jesd51 for test method and conditions table 12 - 32pin t qfn package thermal data
phy1078 - 01 - rd - 1.2 datasheet page 53 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1 - 408 - 601 - 1000 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc . 10. contact information for technical support, contact maxim at www.maxim - ic.com/support . disclaimer this datasheet contains preliminary information and is subject to change. the phy1078 - 01 contains circuitry to aid the implementation of eye safety functions in equipment using laser devices. phyworks ltd accepts no liability for failure of this function in this product nor for injury to persons as a result of use of this product. testing of the functionality of eye safety circuits in equ ipment using this product is the responsibility of the manufacturer of the equipment. this document does not transfer or license any intellectual property rights to the user. phyworks ltd assumes no liability or warranty for infringement of patent, copyright or other intellectual property rights through the use of this product . phyworks ltd assumes no liability for fitness for particular use or claims arising from sale or use of its products. phyworks ltd products are not intended for use in life critical o r sustaining applications.

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